(5.1) Introduction

Chapter 4 introduced the basic building blocks of a computer: transistors, gates, and circuits. This chapter puts those blocks together to build the major sub-systems of a computer.

(5.2) The Components of a Computer System

The earliest computing devices were programmed by punching up a deck of IBM cards and/or wiring up a plug-board. In 1946, John von Neumann suggested it would be better to store the program for a computing device in the same memory as its data so it could fetch its instructions at a fast rate and also operate on its own program if need be. We call this the stored program concept.

Figure 5.2 shows the major sub-systems of a computer with the Von Neumann Architecture. The architecture has a Memory holding both data and instructions to be executed by a computer; a Processor comprising an Arithmetic-Logic Unit (ALU) to operate on the data under control of a Control Unit executing instructions read from memory one at a time; and Input-Output devices to input data and programs from the outside world and to send results to the outside world.

(5.2.1) Memory and Cache: The state of each memory bit is held in a bi-stable device called a flip-flop. There are many different ways to implement a flip-flop from the basic logic gates - the following diagram shows a flip-flop built from a NOT-gate, an AND-gate, and an OR-gate:

Raising the S input of this flip-flop to the 1-value sets the state of its stored bit, Q, to the 1-state. Raising the R input to the 1-value resets the state of Q to the 0-state. When S = R = 0 the flip-flop acts like a memory and holds the current state of its stored bit, Q. The computer should never try to both set and reset the flip-flop at the same time; i.e., it should never raise both inputs S and R to the 1-value simultaneously.

There are only two inputs, S and R, in this circuit but to see how the flip-flop behaves we must also consider the current state of the stored bit, Q, and draw a truth table with 8 rows:

From the truth table we see that the flip-flop behaves like it should:

• if S = R = 0 then the new state of Q equals its current state so the flip-flop acts like a memory and holds its current state;
• if S = 0 and R = 1 then the new state of Q = 0 so the flip-flop forgets its current state and goes to the 0-state; and
• if S = 1 and R = 0 then the new state of Q = 1 so the flip-flop forgets its current state and goes to the 1-state.

The metric system of measurements uses certain prefixes for certain powers of ten:

The computer field only does this with memory capacities - all other quantities are measured with powers of ten. For example, an 800-megahertz clock emits exactly 800,000,000 clock ticks per second and a network link with a 10-megabyte/second bandwidth transmits exactly 10,000,000 bytes per second across the link.

A text string of m characters occupies m successive bytes of a RAM with each byte holding the ASCII code for one character. For example, the 10-character string, KENT STATE, might occupy bytes 160 through 169 of a RAM as follows:

The Memory Unit also has a Memory Address Register (MAR) and a Memory Data Register (MDR) for communication with other parts of the computer. The MAR holds the N-bit address of a memory cell and the MDR holds the data being fetched from that cell or the data being stored into that cell. The size of the MDR is some multiple of W bits and usually agrees with the size of the processor: e.g., a 32-bit processor can fetch or store 32 memory bits at one time so the MDR holds 4 bytes.

A memory fetch operation retrieves data from a storage location of the RAM using the following algorithm:

1. Copy the address of the storage location into the MAR.
2. Decode the contents of the MAR to select the desired storage location of the RAM.
3. Copy the contents of that storage location into the MDR.

1. Copy the address of the storage location into the MAR.
2. Copy the value to be stored into the MDR.
3. Decode the contents of the MAR to select the desired storage location of the RAM.
4. Copy the contents of the MDR into that storage location.

A large RAM is usually too slow for the processor so modern computers use a small fast cache memory as well as the RAM. Most computer programs exhibit a property called locality of reference: if the program has recently referenced a particular storage location in the RAM it will most likely want to reference the same location (or its neighbors) in the near future. The cache memory holds recently-referenced memory items and their neighbors so future references to these items can be performed much faster.

A Read-Only Memory (ROM) is a RAM without the store operation: its contents are fixed when it is built. One common use of a ROM is to initialize a computer properly whenever it is turned on.

(5.2.2) Input/Output and Mass Storage: There is a wide variety of input/output (I/O) devices that computers connect to:

• input devices like keyboards, mice, and microphones that people use to enter data into computers;
• output devices like screens, printers, and loudspeakers that computers use to present data to people; and
• mass storage systems like floppy disks, hard disks, optical disks, and tapes on which computers can store and retrieve data.

Tapes are sequential access storage devices (SASDs). To find a particular data record on the tape the computer starts at the beginning of the tape and examines the records one at a time until it finds the one sought.

I/O devices are much slower than the other subsystems of a computer so the I/O controllers contain buffers to temporarily hold I/O data. The processor executes instructions while I/O data is being transferred.

(5.2.3) The Arithmetic/Logic Unit: The arithmetic/logic unit (ALU) is usually shown as a vee-shaped block to emphasize the fact that it combines two input numbers, A and B, with an arithmetic operation (add, subtract, multiply, etc.) to produce one number as a result. The operation is specified by a set of control lines fed by the Control Unit:

The ALU can also compare the two input numbers to see if A is Greater-Than, EQual to, or Less-Than B - for this operation the ALU sets one of the three condition-code bits (GT, EQ, or LT) to the 1-state.

To speed up arithmetic, modern computers couple the ALU with a set of very fast memory cells called registers. Figure 5.11 shows such a datapath with an ALU coupled to 16 registers, R0, R1, ..., R15. The organization is very flexible; for example, the ALU can subtract the value in any register from the value in any register and store the difference into any register. Storing the result of an ALU operation into a register overwrites the previous value stored in that register.

In a b-bit processor each register holds b bits and the ALU performs operations on b-bit data items (b is usually 32 or 64.)

(5.2.4) The Control Unit: The stored program concept means that machine instructions are stored in memory as sequences of binary bits. The control unit:

1. fetches the next instruction from memory;
2. decodes the instruction to determine what is to be done; and
3. executes the instruction by issuing the appropriate control signals to the ALU, the memory, and the I/O controllers.

Each instruction is written in machine language as a sequence of 0-bits and 1-bits with a format like:

Each operation in the instruction set of the computer is assigned a unique unsigned-integer operation code (or opcode). For example, opcode 0 might specify the ADD operation, opcode 1 might specify the COMPARE operation, etc. An opcode field of k bits can specify any one of 2^k different operations.

The address fields specify the locations of the source operands and the result of the operation. For example, an instruction to subtract the contents of register R2 from the contents of register R1 and put the difference in register R3 might look like:

where 0101 is the opcode for subtraction and each 4-bit address field specifies one of the sixteen registers. Address fields specifying memory locations are much longer since it takes an n-bit address to specify one of the locations in a 2ⁿ-byte RAM. Some processors use only two address fields for arithmetic operations - the result of an operation overwrites one of the source operands.

In the seventies and the eighties the typical processor had several hundred opcodes. The add operation, for example, might have three different opcodes:

• ADD - to add one memory word to another memory word;
• ADD3 - to add two memory words together and put their sum into a third memory word; and
• ADDR - to add two registers together and put their sum into a third register.

These processors had variable-length instructions. For example, the ADD3 instruction required many more bytes than the ADDR instruction.

Machine languages for modern processors are much simpler with less than 50 operations. These machines are called Reduced Instruction Set Computers or RISC machines. Fixed-length instructions (usually 32 bits) are used and arithmetic operations only use register operands. Even though a RISC machine must execute more instructions to perform a typical algorithm, each instruction runs much faster so the running time of the algorithm is less.

There are four basic classes of instructions:

1. Data Transfer: to move operands between registers and memory words, etc.
2. Arithmetic: to add, subtract, multiply, divide, and logically combine operands.
3. Compare: to compare two values and set the states of condition code bits depending on outcome of the comparison.
4. Branch: to alter the flow of control through the instructions based on the states of the condition code bits.

(5.3) Putting All the Pieces Together: Figure 5.18 shows the organization of a Von Neumann computer with a number of ALU registers: R0, R1, R2, R3, ...

Figure 5.19 shows a hypothetical instruction set for a Von Neumann computer:

The control unit uses the following algorithm to execute a program.

1. Copy the address of the instruction in the PC to the MAR.
2. Initiate a fetch operation in the memory to put a copy of the instruction in the MDR.
3. Copy the instruction in the MDR to the instruction register (IR.)
4. Increment the value in the PC to the address of the following instruction.

Execute Phase: The steps in the execute phase depend on the opcode of the instruction. The steps for some of the instructions in figure 5.19 are shown below:

• LOAD X - Load register R from memory location X
  1. Send a copy of the address of X in the IR to the MAR.
  2. Initiate a fetch operation in the memory to put a copy of X's value in the MDR.
  3. Copy the contents of the MDR into register R.

• STORE X - Store register R into memory location X
  1. Send a copy of the address of X in the IR to the MAR.
  2. Send a copy of the contents of register R to the MDR.
  3. Initiate a store operation in the memory to copy the contents of MDR into memory location X.

• ADD X - Add the contents of memory location X to register R
  1. Send a copy of the address of X in the IR to the MAR.
  2. Initiate a fetch operation in the memory to put a copy of X's value in the MDR.
  3. Send a copy of the contents of register R to input A of the ALU.
  4. Send a copy of the MDR contents to input B of the ALU.
  5. Initiate an Add operation in the ALU.
  6. Copy the ALU result into register R.

• JUMP X - Jump to the instruction in memory location X
  1. Send a copy of the address of X in the IR to the PC.

• COMPARE X - Compare the contents of memory location X to register R and set the condition codes appropriately
  1. Send a copy of the address of X in the IR to the MAR.
  2. Initiate a fetch operation in the memory to put a copy of X's value in the MDR.
  3. Send a copy of the contents of register R to input A of the ALU.
  4. Send a copy of the MDR contents to input B of the ALU.
  5. Initiate a compare operation in the ALU to set the condition codes.

• JUMPGT X - If condition code GT = 1, then jump to the instruction in memory location X; else just go to the next instruction in the program
  1. If condition code GT = 1, then send a copy of the address of X in the IR to the PC; else do nothing.

Figure 5.20 graphs processor speeds from the mid-1940s to the present. At first processor speeds grew exponentially - quadrupling about every three years. But lately the growth rate has been slower. To get higher processing speed several processing elements are coupled together in a parallel processor. Parallel processors come in two different flavors: SIMD and MIMD.

SIMD: Figure 5.21 is a block diagram of a Single-Instruction-Multiple-Data (SIMD) processor - several ALUs (usually in the thousands) reading and writing data in their own local memories under command of a single control unit executing instructions from a single program. For example, an ADD instruction in the program will cause every ALU to perform an ADD operation on its own data. Unfortunately, the figure doesn't show the interconnection network between the ALUs that every SIMD processor has.

MIMD: Figure 5.22 is a block diagram of a Multiple-Instruction-Multiple-Data (MIMD) processor - several processors (each with its own ALU and control unit) execute instructions from their own programs in their own local memories. For example, while some processors are executing ADD instructions others might be executing SUB instructions.

SIMD vs. MIMD: The single control unit in a SIMD processor keeps all ALUs in lock-step. This simplifies communication of data between the ALUs - a Data Transfer instruction in the program:

• commands every ALU to send a data item to the interconnection network;
• commands the network to perform a certain permutation on the set of data items; and
• commands every ALU to receive a data item from the network.

Inter-processor communication in a MIMD processor is much slower. For example, to send a data item from processor A to processor B, the program in A must be synchronized with the program in B so B expects to receive the item when A sends it.