CS 68191 Masters Seminar / CS 89191 Doctoral Seminar
Spring 2008
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency
in an Associative SIMD Processor
Kevin Schaffer
(Doctoral Student Presentation)
The performance of SIMD processors is often limited by the time it
takes to transfer data between the centralized control unit and the
parallel processor array. This is especially true of hybrid SIMD
models, such as associative computing, that make extensive use of
global search operations. Simulation results indicate that a
combination of pipelining and fine-grain hardware multithreading can
improve performance significantly, even for hundreds or thousands of
processing elements.