Selected Recent Papers

Parallel Processing & Distributed Computing

"Implementing Associative Processing: Rethinking Earlier Architectural Decisions"", Robert A. Walker, Jerry Potter, Yanping Wang, and Meiduo Wu, in Proc. of the 16th International Parallel and Distributed Processing Symposium (Workshop in Massively Parallel Processing), abstract on page 195, full text on CDROM, April 2001. (Unofficial version: pdf)
"Flexible Parallel Processing in Memory: Architecture + Programming Model ", Nael B. Abu-Ghazaleh, Philip A. Wilsey, Jerry Potter, Robert Walker, and Johnnie Baker, in Proc. of the Third Petaflop Workshop. February 1999. (Official version is here, unofficial version: pdf ps)

Design Space Exploration

"Efficient Optimal Design Space Characterization Methodologies", Stephen A. Blythe and Robert A. Walker, to appear in ACM Transactions on Design Automation of Electronic Systems. (Unofficial version: pdf ps)
"Efficiently Searching the Optimal Design Space", Stephen A. Blythe and Robert A. Walker, in Proc. of the 9th Great Lakes Symposium on VLSI, pages 192-195. IEEE, Ann Arbor, Michigan, March 1999. (Unofficial version: pdf ps)
"Toward a Practical Methodology for Completely Characterizing the Optimal Design Space", Stephen A. Blythe and Robert A. Walker, in Proc. of the 9th International Symposium on System Synthesis, pages 8-13. ACM / IEEE, La Jolla, California, November 1996. (Unofficial version: pdf ps)
"A Solution Methodology for Exact Design Space Exploration in a Three-Dimensional Design Space", Samit Chaudhuri, Stephen A. Blythe, and Robert A. Walker, IEEE Transactions on VLSI Systems 5(1):69-81, March 1997. (Unofficial version: pdf ps)
"An Exact Methodology for Scheduling in a 3D Design Space", Samit Chaudhuri, Stephen A. Blythe, and Robert A. Walker, in Proc. of the 8th International Symposium on System Synthesis, pages 78-83. ACM / IEEE, Cannes, France, September 1995. (Official version at ACM is here; unofficial version: pdf ps)

Bounding Algorithms

"Bounding Algorithms for Design Space Exploration", Samit Chaudhuri and Robert A. Walker, in Proc. of the 9th Great Lakes Symposium on VLSI. pages 234-235. IEEE, Ann Arbor, Michigan, March 1999. (Unofficial version: pdf ps)
"Computing Lower Bounds on Functional Units Before Scheduling", Samit Chaudhuri and Robert A. Walker, IEEE Transactions on VLSI Systems 4(2):273-279, July 1996. (Unofficial version: pdf ps)
- Expanded version with proofs: Renssleaer CS Dept. Tech Report #95-13 (pdf ps)
"Computing Lower Bounds on Functional Units Before Scheduling", Samit Chaudhuri and Robert A. Walker, in Proc. of the 7th International Symposium on High-Level Synthesis, pages 36-41. ACM / IEEE, Niagara-on-the-Lake, Ontario, May 1994. (Unofficial version: pdf ps)

Scheduling

"Analyzing and Exploiting the Structure of the Constraints in the ILP Approach to the Scheduling Problem", Samit Chaudhuri, Robert A. Walker, and John E. Mitchell, IEEE Transactions on VLSI Systems 2(4):456-471, December 1994. (Unofficial version: pdf ps)
"ILP-Based Scheduling with Time and Resource Constraints in High-Level Synthesis", Samit Chaudhuri and Robert A. Walker, in Proc. of the 7th International Conference on VLSI Design, pages 17-25. VLSI Society of India / ACM / IEEE, Calcutta, India, January 1994. (Unofficial version: pdf ps)
"The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem", Samit Chaudhuri, Robert A. Walker, and John E. Mitchell, in Proc. of the 1993 International Conference on Computer Design, pages 25-29. IEEE, Cambridge, Massachusetts, October 1993. (Unofficial version: pdf ps)

Tutorials

"Introduction to the Scheduling Problem", Robert A. Walker and Samit Chaudhuri, IEEE Design and Test, 12(2):60-69, Summer 1995. (Official version at IEEE CS is here; unofficial version: pdf ps)

Computer Science / Engineering Education

"A Practical One-Semester 'VLSI Design' Course for Computer Science (and Other) Majors", Robert A. Walker, in Proc. of the ACM Special Interest Group on Computer Science Education Technical Symposium, pages 237-241. ACM, New Orleans, Louisiana, March 1999. (Unofficial version: pdf ps)

My Historical Origins (Selected Old Papers)

"Behavioral Transformation for Algorithms Level IC Design", Robert A. Walker and Donald E. Thomas, IEEE Transactions on Computer-Aided Design 8(10):1115-1128, October 1989. (Unofficial version: pdf ps)
- Summary of my PhD dissertation.
"The System Architect's Workbench", D.E. Thomas, E.M. Dirkes, R.A. Walker, J.V. Rajan, J.A. Nestor, and R.L. Blackburn, in Proc. of the 25th Design Automation Conference, pages 337-343. ACM / IEEE, Anaheim, California, June 1988. (Unofficial version: pdf ps)
- Overview of our project, just before I finished my PhD.
"A Model of Design Representation and Synthesis", Robert A. Walker and Donald E. Thomas, in Proc. of the 22nd Design Automation Conference, pages 453-459. ACM / IEEE, Las Vegas, Nevada, June 1985. (Unofficial version (scan): pdf)
- Preliminary work while looking for a dissertation topic; this paper was nominated for a Best Paper Award.
"Automatic Data Path Synthesis", Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, and Robert A. Walker, IEEE Computer, 16(12):59-70, December 1983. (Unofficial scan of published version: pdf)
- Overview of one of the first high-level synthesis systems, just after I finished my Masters.
"Behavioral Level Transformation in the CMU-DA System", Robert A. Walker and Donald E. Thomas, in Proc. of the 20th Design Automation Conference, pages 788-789. ACM / IEEE, Miami, Florida, June 1983. (Unofficial version (scan): pdf)
- This was my very first conference paper; it discussed my Master's work.

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